The present invention relates to a semiconductor device and, more specifically, relates to the arrangement of semiconductor chip pads connected to package terminals and the connections between the arranged pads and the package terminals.
Recently, as the operation speed of semiconductor devices has been increased and large-scale integration has been promoted, the size of the packages of semiconductor devices has been decreased so as to reduce the overall size of the semiconductor devices. For example, a dynamic random access memory (DRAM) with a large memory capacity of one gigabit that can be mounted on a small package has been developed. The small package employs a surface mounted ball grid array (BGA) including solder balls disposed on a package substrate. The arrangement of the solder balls in the BGA is standardized. Thus, the arrangements of signal pads and VDD/VSS pads included in the chip have to correspond to the standardized arrangement of the solder balls in the BGA.
Various different types of VDD and VSS pads are provided in the DRAM chip in a manner such that they are separated from each other so that noise generated at circuit blocks in the VDD and VSS pads does not affect other VDD and VSS pads. For example, an external power source and ground (GND) for a word-line voltage generator circuit (VDDP/VSSP) and an external power source and GND for a sense amplifier circuit (VDDDSA/VSSSA) are separated since noise generated at a power source that requires a large current affects other types of power sources. However, in a package, various types of ball lands corresponding to various types of power sources do not exist, but only one type of ball land is provided and is aggregated in the package pathway into the same electrical potential. In other words, the various types of power sources (e.g., VDD/VSS, VDDP/VSSP, and VDDDSA/VSSSA) is collectively treated as one type of power source (i.e., VDD/VSS) in the package.
FIGS. 1 to 3 are schematic plan views illustrating the power source-to-GND connection of such a known DRAM chip and package. FIG. 1 illustrates an overall schematic view. FIG. 2 illustrates a detailed view of the area at the right edge. FIG. 3 illustrates a detailed view of the area at the left edge. The semiconductor device is a resin-sealed BGA constructed by stacking a package substrate 9 on a DRAM chip 1 with an elastomer interposed therebetween. The DRAM chip 1 and the package substrate 9 are bonded together with the elastomer. Solder balls are provided on the package substrate 9 as connection pins to provide connection with the outside.
A single row of a plurality of pads 2 is provided on the DRAM chip 1. The elastomer has an elastomer opening 3 corresponding to the area where the pads 2 are disposed on the DRAM chip 1. The package substrate 9 includes a TAB tape having a plurality of ball lands 5 and leads 6. The TAB tape has a tape opening 4 corresponding to the elastomer opening 3. The tips (also referred to as “TAB leads”) of the leads 6 in the tape opening 4 are bonded to the pads 2. The TAB leads are connected to the pads 2 of the DRAM chip 1. Accordingly, the pads 2 are connected to the ball lands 5, where solder balls are provided, via the leads 6. The elastomer opening 3 and the tape opening 4 are filled with sealing resin.
A pair of a VDD pad and a VSS pad, which are disposed adjacent to each other, is provided for each different type of power supply on the DRAM chip 1 to reduce loop inductance. As the entire package, a plurality of different types of power sources and GNDs having the same electrical potential are disposed alternately. Since the pads are arranged in a single row, leads can be connected to either one of the opposing sides of the pad row. A power supply lead 6-1 from a VDD pad can be connected to a ball land 5-1 on the first side (hereinafter referred to as the “upper side”) of the pad row. Similarly, a GND lead 6-2 from a VSS pad can be connected to a GND ball land 5-2 on the second side (hereinafter referred to as the “lower side”) of the pad row. In this way, leads from the pads 2 can be connected to power supply and GND ball lands 5 in the vicinity of the respective pads 2.
In the area at the right edge of the DRAM chip 1, a power supply (VDD) ball land 5-1 is provided on the upper side and a GND (VSS) ball land 5-2 is provided on the lower side. In this area, a power supply lead 6-1 is lead out upwards, whereas a GND lead 6-2 is lead out downwards. As shown in the detailed diagram in FIG. 2, from right to left on the DRAM chip 1, an external power supply (VDDSA/VSSSA) pads for a sense amplifier circuit, an external power supply (VSSP/VDDP) pads for a word-line voltage generator circuit, an external power supply (VDD/VSS) pads for general use, and an external power supply (VSSI/VDDI) pads for an internal step-down circuit are provided.
VDD pads and VSS pads are disposed adjacent to each other in pairs. A power supply (VDD) ball land 5-1 on the upper side is connected to pads 2 via a power supply lead 6-1 by bonding the tips of the TAB leads of the power supply lead 6-1 to the pads 2. Similarly, a GND (VSS) ball land 5-2 on the lower side is connected to pads 2 via a GND lead 6-2 by bonding the tips of the TAB leads of the GND lead 6-2 to the pads 2.
On the other hand, at the left edge area illustrated in FIG. 3, power supply ball lands and GND ball lands that can be connected to the pads are not provided in the lower left area. Therefore, the route of a power supply lead 6-1 led out downwards becomes long, i.e., almost one-quarter of the perimeter of the package. If, instead, a GND lead is led out downwards, the GND lead will have to be connected to a GND ball land 5-2 near the right edge, and the route of the lead will be even longer, i.e., almost half the perimeter of the package.
Recently, chips having a large area have been developed in response to the significant increase in memory capacity. However, because of limitations imposed by mounting a DIMM, a reduction in the area where pads are disposed has been required, even for a large-area chip. Therefore, an arrangement in which a plurality of memory array blocks is disposed at the periphery whereas two rows of pads are provided in the central area of the chip is proposed. However, when the pads are arranged in two rows and the VDD and VSS pads are arranged in the same manner as the above-described arrangement, the direction to lead out the leads cannot be selected in the same manner as when pads are arranged in a single row. Leads can only be lead out to the upper side from center pads in the upper row, whereas leads can only be lead out to the lower side from center pads in the lower row. In other words, the direction of the leads be lead out cannot be freely selected. As a result, leads to be lead out from the VDD and the VSS pads disposed at left ends of the center pad rows will have to be routed along an extremely long path, such as half the perimeter of the package. Consequently, some of the leads may not be able to reach ball lands.
As shown in FIG. 4, among the pads disposed in an order of “VSS pad, VDD pad, VDD pad, and VSS pad” from the right end of the upper row, the leftmost VSS pad cannot be connected to a ball land. Similarly, among pads disposed in an order of “VSS pad, VDD pad, VDD pad, and VSS pad” from the left end of the lower row, the rightmost VSS pad cannot be connected to a ball land.
FIG. 5 illustrates a case in which plated leads is used. For DRAMs, multi-bit products are provided in series. For example, a four-bit (×4) product and an eight-bit (×8) product are provided as bonding options. In a 4× product, compared to a 8× product, the higher order four-bit pins, among data (DQ) pins, are no-connection (NC) pins. An NC ball land that is a no-connection (NC) pin is connected to the edge of the package substrate by a plated lead. Since the plated lead is lead out toward the edge of the package substrate, it bypasses other plated leads. Therefore, for a 4× product, the routes of the leads are complex and the total length of the leads is long.
In this way, for a large-scale integrated semiconductor device having two rows of center pads in a chip, problems such as the total length of the leads connecting the ball lands of the package and the pads of the chip increasing or problems such as not being able connect the ball lands and pads may occur. In particular, such a problem is likely to occur in power supply leads provided separately for various different types of power supplies. The positions of the pads for difference types of power supplies, such as an external power supply (VDDSA/VSSSA) for a sense amplifier circuit or an external power supply (VDDP/VSSP) for a work-line voltage generator circuit, must be arranged carefully such that the power supply does not act as a noise source affecting signal lines and such that the power supply can efficiently supply electrical power to the entire chip. As described above, there are problem in the wiring for a semiconductor device having various different types of power supplies in that the ball lands of the package and the pads of the chip cannot be connected at low resistance with short leads.
Patent documents describing power supply wiring and pad arrangement on a chip include the following:
Japanese Unexamined Patent Application Publication No. 11-340438;
Japanese Unexamined Patent Application Publication No. 09-107081;
Japanese Unexamined Patent Application Publication No. 05-343634; and
Japanese Unexamined Patent Application Publication No. 05-251495.
According to Japanese Unexamined Patent Application Publication No. 11-340438, the power supply is reinforced by providing power supply leads as a mesh in the chip. According to Japanese Unexamined Patent Application Publication No. 09-107081, two rows of center pads arranged in a checkered pattern include a plurality of power supply pads. According to Japanese Unexamined Patent Application Publication No. 05-343634, memory arrays are provided at the periphery and two rows of pads are provided in the center so as to facilitate bit switching. According to Japanese Unexamined Patent Application Publication No. 05-251495, two types of semiconductor devices include two rows of center pads having a symmetrical pin arrangement by a bonding option.
However, these documents do not discuss the problems in which the power supply-to-GND connection between the package and the chip may become complex or connection may not be established at all. Therefore, solutions for such problems are not provided in these documents.
As described above, in a large-scale integrated semiconductor device, it is desirable to provide two rows of pads in the center of the semiconductor chip. However, since the pads arranged in two rows are separated into the pads in the upper row and the pads in the lower row, the pads in each row can only use the wiring area of the package substrate on the same side of that row. For this reason, connections between the ball lands of the package and the pads of the chip become complex. Since various different types of power supplies are used inside the semiconductor device, pads for particular types of power supplies are collectively disposed at the end of the center pads so as to prevent noise from being generated between power supplies. As a result, the connections between the ball lands of the package and the pads of the chip become even more complex, and the total length of the leads become long, or connection cannot be established at all. Consequently, there is a problem in that the ball lands of the package and the pads of the chip cannot be connected at low resistance with short leads.